The invention relates to the general field of photolithography with particular reference to etching damascene wiring patterns in which via hole diameters are less than about 0.15 microns.
The invention relates to the manufacturing of Ultra Large Scale Integrated Circuits (ULSI) wherein the interconnection structures consist of inlaid conductive metal wiring and conductive contact and via holes formed using a dual damascene process. This invention describes a method of forming a dual damascene structure whose dimensions are less than those obtainable when using conventional photo lithography techniques.
Subtractive etching methods for forming interconnects have been used in the integrated circuit industry for a long time. Such methods involve formation of contact or via holes in a dielectric layer and then depositing a metal film such as aluminum or its alloy by a sputtering technique. This metal layer is then patterned using a photolithography mask and the metal is etched to form a wiring pattern. Multiple wiring pattern layers can be formed by deposition of an interlayer dielectric and connection of metal wiring by-via hole patterns.
The switch from aluminum and its alloys to copper interconnect schemes brought about changes in the interconnect process technology. Since etching of copper is difficult when using subtractive etching methods, xe2x80x98damascene/dual damascenexe2x80x99 processing approaches have evolved. In the damascene process a trench is cut in the dielectric for metal wiring and contact and/or via holes are formed in the dielectric for wiring interconnect. Several different techniques of forming dual damascene structures are known, some of which we describe below:
Prior art method no. 1:
Referring now to FIG. 1a, substrate 11 is coated with dielectric layer 12 and trench 13 is etched therein. This is followed (FIG. 1b) by the application of photoresist layer 14 which is patterned to provide an etch mask with opening 15. All unprotected dielectric is then etched down to the level of substrate 11, thereby forming via hole 16, as seen in FIG. 1c. After the resist has been stripped, the via hole and trench are filled with metal 17 to form the damascene structure (referred to as xe2x80x98dualxe2x80x99 because both hole and trench formation are involved) seen in FIG. 1d. 
Prior art method no. 2:
Here, formation of via hole 16 is the first step, as shown in FIG. 2a. Then, as seen in FIG. 2b, photoresist 24 is laid down and patterned to define the trench (FIG. 2c). After trench etching and resist stripping, the trench and via are filled with metal 17 (FIG. 2d).
Prior art method no. 3:
This variation begins with deposition of silicon nitride layer 31 onto dielectric 12, as seen in FIG. 3a, followed by photoresist layer 34 which is patterned to define the via hole. Then the silicon nitride is selectively removed to form hard mask 131 (FIG. 3b) and second dielectric layer 32 is laid down (FIG. 3c). A second photoresist layer 35 is then applied over layer 32 and patterned to define the trench (FIG. 3d). A single etch step is then used to form both the trench 33 and the via hole 36 (FIG. 3e). Then, as before, all resist is removed and trench and via are filled with metal 17 (FIG. 3f).
Prior art method no. 4:
In this fourth prior art approach, the dielectric layer 12 is also coated with silicon nitride 31, following which a layer of positive photoresist 41 is laid down and patterned to define via hole 15 (FIG. 4a). A layer of negative photoresist 42 is deposited over patterned layer 41 and is itself patterned to define trench 13. Because of their different chemistries, patterning of 42 does not impact layer 41 as shown in FIG. 4b. Then, silicon nitride etch stop layer 31 is selectively removed and simultaneous etching of both resists as well dielectric layer proceeds so that trench 33 and via 36 are both formed in a single etching operation (FIG. 4c). Then, as before, all resist is removed and trench and via are filled with metal 17 (FIG. 4d).
While all of these prior art methods are widely used, they all share a single difficulty, namely that they are ineffective for etching via holes having a diameter less than about 0.15 microns. This is because contact and via holes of size 0.18 micron and below are becoming so small in dimension that it is difficult to pattern them (using conventional photolithography techniques) with consistent accuracy and the process repeatability required for ULSI devices. With current photolithography techniques it is very difficult to form via/hole structure without the use of lithography enhancement techniques such as off-axis illumination and attenuated phase shift masking.
Approaches that have been taken towards dealing with this problem include shrinking the via size by deposition of dielectric in the hole opening as taught by Lin in U.S. Pat. No. 05,753,967, and a self-aligned method to form a narrow via (Lu U.S. Pat. No. 5,789,316). In a routine search of the prior art, the following additional references of interest were also found:
In U.S. Pat. No. 5,877,076, Dai describe atwo step process based on a combination of positive and negative resists. Nguyen et al. (U.S. Pat. No. 6,043,164), Dai (U.S. Pat. No. 5,976,968), and Nguyen et al. (U.S. Pat. No. 5,936,707) all disclose two photoresist/one etch dual damascene processes. In U.S. Pat. No. 5,935,762, Dai et al. show a 2 resist layer dual damascene process while, in U.S. Pat. No. 5,882,996, Dai shows a dual damascene bi-layer photoresist process.
It has been an object of the present invention to solve the problem of how to pattern via/contact holes less than 0.15 um in a damascene structure.
Another object of the invention has been to reduce the process to two lithography steps and one etching step.
These objects have been achieved by the use of e-beam patterning techniques for forming the contact and via holes while using deep ultra violet photolithography patterning techniques for forming the trenches. A simplified process scheme is described wherein contact/via holes are formed first on a solvent developable e-beam resist and the trench pattern is then formed on an aqueous developable photoresist coated on top of said e-beam resist.